The past few years have seen a dramatic growth in the demand for data services over wireless communication channels. Recent wireless standards have evolved to meet the needs of increased number of users as well as increased throughput per user. The tutorial will present an overview of some common techniques that improve the efficiency of high speed packet data links in cellular systems. We will review some basic techniques such as link adaptation, incremental redundancy, hybrid ARQ, and smart scheduling, and then will look at some recent progress in the areas of MIMO transceiver design, interference mitigation, and resource allocation.

Power transformer in service, go through natural ageing under operating stress conditions as well as accelerated ageing due to contamination and abnormal service conditions such as overloading, short-circuit in System or over voltage. A power transformer outage can cause wide disruption of power. Among the costliest equipment in Power system, the lead-time for repair or replacement of Power Transformer is several months. Hence, Utilities are striving to improve the life management of equipment and reliability of supply by continuous monitoring of the transformer and diagnose its condition for pre-emptive action.

The workshop will provide an overview of the current monitoring methods, their limitations and some of the research work going on worldwide aiming at cost effective diagnostics and estimation of the loss of life of the transformer. The workshop, with faculty drawn from IIT-Madras, is essentially targeted at postgraduate and research students in Power apparatus and Systems area and will be informative to Utility engineers responsible for the life-management of substation equipment.

Current digital designs use multiple subsystems that interact in many complex ways. These large designs are typically implemented using hardware description languages (HDLs) like Verilog and VHDL and more recently using languages like System C and System Verilog. With any complex system a natural question to ask is how correct the system is. Many tools are available to verify whether the design is functionally correct and whether it complies with the original specification. This tutorial deals with methodologies for verifying current day digital designs.
Verification of large designs is a complex task in itself. Design teams typically develop test strategies even as early as the code development stage. Developing a test strategy that tests for various corner cases is specifically a very demanding task. Typically, a designer who has extensive domain expertise is called upon to create the test plan that is translated to vast amounts of code written by large verification teams. More than half the design resources and > 70% of time to develop a product is used by the verification phase of chip design due to the difficulty in finding a good strategy to check all cornet cases. Current trends are to make sure the design is “correct by construction” and verify the design right from the early stages. Effective time to market is achieved only when the design is done “right the very first time”. Such a goal is also very important to critical designs that are used in avionics, nuclear applications and in the health industry.
The objective of this tutorial is to create awareness on testing large scale designs in a highly automated fashion.